1 ps8190d 05/04/00 b cc 1 1 2 3 4 5 6 7 gnd 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 a 12 a biasv 1 a 15 a 1 a 17 a 1 a 8 19 a 110 a 21 a 22 a v 23 a 24 a 25 a 26 a 27 a 28 a 29 a 210 a 1b5 1 b 1 1 oe 12 b 13 b 1 b4 gnd 1 b 6 17 b 18 b 1 b 9 1 b 10 gnd 22 b 21 b 23 b gnd 24 2 b 5 26 b 2 b 7 2 b 8 29 b 2 b 10 2 oe 1 a 3 4 6 1a10 1a1 1oe 2a1 2oe 2a10 24 13 47 48 12 2 46 36 35 25 1 biasv 1b1 1b10 2b1 2b10 sw sw sw sw b a oe product description pericom semiconductor?s pi3b series of logic circuits are produced using the company?s advanced 0.35 micron cmos technology. the PI3B16215 provides 20-bits of high-speed bus switching. low on-state resistance of the switch allows connections to be made with minimal propagation delay. the device also precharges the b-port to a user-selectable bias voltage (biasv) to minimize live- insertion noise. the device is organized as dual 10-bit bus switches with individual output-enable (oe) inputs. when oe is low, the corresponding 10-bit bus switch is on and port a is connected to port b. when oe is high, the switch is open, a high-impedance state exists between the two ports, and port b is precharged to biasv through the equivalent of a 10-k w resistor. to ensure the high-impedance state on power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver connected to oe. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features ? near zero propagation delay ?5 w switches connect between two ports ? fast switching speed: 4.5ns max. ? permits hot insertion ? isolation during power-off conditions ? b-port outputs are precharged by bias voltage to minimize signal distortion during live insertion ? package options include: ? 48-pin 150-mil wide plastic bqsop (b) ? 48-pin 240-mil wide plastic tssop (a) ? 48-pin 300-mil wide plastic ssop (v) product pin configuration logic block diagram 3.3v, hot insertion, 20-bit fet busswitch w/precharged outputs PI3B16215 48-pin a,b,v
2 ps8190d 05/04/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16215 3.3v, hot insertion, 20-bit fet busswitch w/precharged outputs e on o i t c n u f lt r o p b = t r o p a hv s a i b = t r o p b , z = t r o p a storage temperature range, t stg ...................................... ?65oc to +150oc supply voltage range, v cc ......................................... ?0.5v to +4.6v bias voltage range, biasv ........................................ ?0.5v to +4.6v input voltage range ........................................................?0.5v to +4.6v dc output current ....................................................................... 120ma power dissipation ............................................................................ 0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) electrical characteristics (over the operating range, t a = ?40c to +85c, v cc = 3.0v to 3.6v) notes: 1. this is the increase in supply current for each input (oe only) that is at the specified voltage level rather than v cc or gnd. 2. measured by the voltage drop between the a and b terminals at the indicated current through the switch. on state resistance is determined by the lower of the voltages of the two (a or b) terminals. r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u v s a i be g a t l o v s a i b 0v c c v v h i e g a t l o v t u p n i l o r t n o c l e v e l - h g i hv c c v 6 . 3 o t v 7 . 2 =2 v l i e g a t l o v t u p n i l o r t n o c l e v e l - w o lv c c v 6 . 3 o t v 7 . 2 =5 . 0 ?8 . 0 v k i e g a t l o v e d o i d p m a l cv c c v 0 . 3 =i i a m 8 1 ? =7 . 0 ?2 . 1 ? i i t n e r r u c t u p n iv c c v 6 . 3 =v i v = c c d n g r o5 m a i h z o t n e r r u c t u p t u o e c n a d e p m i h g i hv c c 0 =v i v = o v 6 . 3 o t 0 =0 1 i o t n e r r u c t u p t u ov c c v 0 . 3 =v , v 4 . 2 = v s a i b o 0 =5 1 . 0a m i c c t n e r r u c y l p p u s r e w o p t n e c s e i u qv c c v 6 . 3 =i o v , 0 = i v = c c d n g r o0 1 m a d i c c ) 1 ( t n e r r u c y l p p u sv c c v 6 . 3 = , v 3 t a t u p n i e n o v t a s t u p n i r e h t o c c r o d n g 0 5 7 c n i e c n a t i c a p a c t u p n iv i 0 r o v 0 . 3 =0 . 3 f p c f f o f f o h c t i w s e c n a t i c a p a c b / a v o r o v 0 . 3 = 0 f f o h c t i w s5 . 8 r n o ) 2 ( e c n a t s i s e r n o h c t i w s v i 0 = i i a m 4 6 =58 w i i a m 4 2 =58 v i v 4 . 2 =i i a m 5 1 =0 15 1 truth table
3 ps8190d 05/04/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16215 3.3v, hot insertion, 20-bit fet busswitch w/precharged outputs switching characteristics over operating range (switching characteristics over recommended operating free-air temperature range unless otherwise noted) r e t e m a r a ps n o i t i d n o c t s e t) t u p n i ( m o r f) t u p t u o ( o t v c c % 0 1 v 3 . 3 = s t i n u . n i m. x a m t d p ) 1 ( b r o aa r o b5 2 . 0 s n t h z p d n g = v s a i b e ob r o a 5 . 4 t l z p v 3 = v s a i b 5 . 4 t z h p d n g = v s a i b 0 . 5 t z l p v 3 = v s a i b 0 . 5 voltage waveforms propagation delay times voltage waveforms enable and disable times test s1 t pd open t plz /t pzl 6v t phz /t pzh gnd parameter measurements (v cc = 2.7 and 3.3v 10%) notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50 w , t r 2.5ns, t f 2.5ns. 4. the outputs are measured one at a time with one transition per measurement. 5. t tpz and t phz are the same as t dis 6. t pzl and t pzh are the same as t en 7. t plh and t phl are the same as t pd figure 2. load circuit and voltage waveforms note: 1. the propagation delay is the calculated rc time of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
4 ps8190d 05/04/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16215 3.3v, hot insertion, 20-bit fet busswitch w/precharged outputs 48-pin tssop (a) package 48-pin bqsop (b) package .014 .0157 bsc 0.40 0.356 .008 0.20 .002 .009 5 ? 0.05 0.25 .079 2.0 .010 0.25 gauge plane .150 .157 x.xx x.xx denotes dimensions in millimeters 3.80 4.00 .228 .244 5.80 6.20 .020 .029 0.50 0.75 .063 1.60 .015 0.381 .386 .394 9.80 10.00 .0051 .009 0.13 0.23 1 48 x 45 ? bsc nom max nom ref .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc
5 ps8190d 05/04/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16215 3.3v, hot insertion, 20-bit fet busswitch w/precharged outputs pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com t r a pe g a k c a p - n i ph t d i we r u t a r e p m e t a 5 1 2 6 1 b 3 i p) 6 5 a ( p o s s t - 6 5l i m - 0 4 2 c o 5 8 + o t c o 0 4 ? b 5 1 2 6 1 b 3 i p) 6 5 b ( p o s q b - 6 5l i m - 0 5 1 v 5 1 2 6 1 b 3 i p) 6 5 v ( p o s s - 6 5l i m - 0 0 3 order information 48-pin ssop (v) package 0.20 0.51 1.01 0.25 0.381 0.635 .008 .008 .016 0-8? 0.20 0.40 .110 2.79 .010 gauge plane .02 .04 .015 .025 x 45? .025 bsc 0.635 .291 .299 x.xx x.xx denotes dimensions in millimeters 7.39 7.59 .395 .420 10.03 10.67 .620 .630 15.75 16.00 .008 .0135 0.20 0.34 1 48 nom. max applications information logic inputs the logic control inputs can be driven up to +3.6v regardless of the supply voltage. for example, given a +3.3v supply, in may be driven low to 0v and high to 3.6v. driving in rail-to-rail? minimizes power consumption. power-supply sequencing proper power-supply sequencing is recommended for all cmos devices. always apply v cc before applying v bias and signals to input/output or control pins. rail-to-rail is a registered trademark of nippon motorola, ltd
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